applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 1 device specification bicmos pecl clock generator S4405 ? features ? generates six clock outputs from 20 mhz to 80 mhz (hfout operates from 10 mhz to 40 mhz) ? allows pecl or ttl reference input ? provides differential pecl output at up to 160 mhz ? 21 selectable phase/frequency relationships for the clock outputs ? compensates for clock skew by allowing output delay adjustment down to 3.125 ns increments ? ttl outputs have less than 400 ps maximum skew ? lock detect output indicates loop status ? internal pll with vco operating at 160 to 320 mhz ? test enable input allows vco bypass for open- loop operation ? maximum 1.0 ns of phase error (750 ps from part to part) ? proven 1.0 micron bicmos technology ? single +5v power supply operation ? 44 plcc package applications ? cmos asic systems ? high-speed microprocessor systems ? backplane clock deskew and distribution general description the S4405 bicmos clock generators allow the user to generate multiphase ttl clocks in the 10C80 mhz range with less than 400 ps of skew. use of a simple off-chip filter allows an entire 160C320 mhz phase- locked loop (pll) to be implemented on-chip. divide- by-two and times-two outputs allow the ability to generate output clocks at half, equal to, or twice the reference clock input frequency. the reference is se- lectable to be either ttl or pecl. by using the pro- grammable divider and phase selector, the user can select from up to 21 different output relationships. the outputs can be phase-adjusted in increments as small as 3.125 ns to tailor the clocks to exact system requirements. implemented in amccs proven 1.0 micron bicmos technology, the S4405 generates six ttl outputs and one differential pecl output. output enables are provided for the various ttl banks, allowing clock control for board and system tests. figure 1. clock generator block diagram phase detector charge pump vco i 0 i 1 mux select ttlref refclk fbclk tsten divsel phsel0 phsel1 reset outen0 outen1 divider and phase control logic hfout x2fout fout0 fout1 fout2 fout3 lock filter digital +5v 0v 14k w analog +5v 0v ?2 peclp mux peclrefn inpsel pecln i 0 i 1s peclrefp
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 2 S4405 functional description functional description this bicmos clock generator is designed to allow the user to generate ttl clocks, in the 10C80 mhz range, with less than 400 ps of skew. implemented in amccs 1.0 m bicmos technology, the internal vco, phase detector, and programmable divider and phase selector allow the user to tailor the ttl output clocks for his/her system needs. the internal vco can operate between 160 to 320 mhz, and the pro- grammability allows the user to generate ttl output clocks in the 10C80 mhz range, and a differential +5v referenced ecl output at 80C160 mhz. the clock generator offers the user the ability to se- lect the appropriate phase relationship among the four fout0C3 ttl clock outputs. the phase selec- tion choices are shown in table 2. the clock generator also allows the user to choose the divide-by ratio between the vco frequency and the frequency of the fout0C3 signals. the vco fre- quency can be divided by 4 when divsel is low, and divided by 8 when divsel is high. the divide ratio between the vco and the pseudo ecl outputs, peclp and pecln, is a fixed divide-by-2. the clock generator also has two output enable in- puts which can be used to control which outputs toggle. outen0 controls the hfout and x2fout outputs, and outen1 controls the fout0C3 out- puts. when the output enables are high, the outputs are disabled, and held in a high state. refclk can be driven by either the ttlref or peclref inputs. the reference clock source is se- lected with the inpsel input. when inpsel is low, the ttlref input is selected as the reference clock. the fout0C3 outputs are the main ttl output clocks that the generator supplies. the frequency of these outputs is determined by the refclk clock frequency and the output clock that is tied to the fbclk input. fout0C3 will be equal to refclk, half of refclk, or twice the frequency of refclk. the x2fout ttl output provides a clock signal that is identical to the fout0 output in the divide-by-4 mode, but twice the fout0 frequency (max. freq. of 66 mhz) in the divide-by-8 mode. the hfout ttl output provides a clock signal that is also in phase with the fout0 output, but at half the fout0 frequency. filter is the analog signal from the phase detector going into the vco. this pin is provided so a simple external filter (a single resistor and one capacitor) can be included in the phase-locked loop of the clock generator. the lock output goes high when the reference clock and fbclk are within 2C4 ns of each other. this output tells the user that the pll is in lock. three pins are included for test purposes. testen allows the chip to use the refclk signal instead of the vco output to clock the chip. this is used during chip test to allow the counters and control logic to be tested independently of the vco. the reset pin initializes the internal counter flip-flops to zeros, but several clock cycles are necessary before the out- puts go to a zero state. the minimum phase delay between fout0C3 sig- nals is a function of the vco frequency. the vco frequency can be determined by multiplying the out- put frequency by the divide-by ratio of four or eight. the minimum phase delay is equal to the period of the vco frequency: m p = 1/vco freq. since the vco can operate in the 160 mhz to 320 mhz range, the range of minimum phase delay values is 6.25 ns to 3.125 ns. table 1 shows various fout/vco fre- quencies and the associated phase resolution. the charge pump and vco portion of the chip use a separate analog power supply. this supply is brought onto the chip through a distinct set of power and ground pins. this supply should be free of digital switching noise. example: in a typical system, designers may need several low- skew outputs, one early clock, one late clock, a clock at half the input clock frequency, and one at twice the input clock frequency. this system requirement fout0C3 divider vco min phase freq select freq resolution 80 mhz 4 320 mhz 3.125 ns 66 mhz 4 266 mhz 3.75 ns 50 mhz 4 200 mhz 5.0 ns 40 mhz 4 160 mhz 6.25 ns 40 mhz 8 320 mhz 3.125 ns 33 mhz 8 266 mhz 3.75 ns 25 mhz 8 200 mhz 5.0 ns 20 mhz 8 160 mhz 6.25 ns table 1. example phase resolution phsel1 phsel0 phase relationship 0 0 all at same phase 0 1 outputs skewed by 90 degrees from each other 1 0 fout1 leads fout0 by minimum phase, fout2 lags fout0 by minimum phase, and fout3 lags fout0 by 90 degrees 1 1 outputs skewed by minimum phase (determined by the divider selection, and the vco frequency) from each other. note: the pecl output is not affected by the phase select inputs. table 2. phase selections
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 3 functional description S4405 can be met by setting phsel1 to 1, phsel0 to 0, and feeding back fout0 to the fbclk input (row 10 of table 3). the result is that fout0 will be phase-aligned to the reference clock, fout1 will lead the reference clock by a minimum phase delay, fout2 will lag the reference clock by a minimum phase delay, fout3 will phase-lag the reference clock by 90 , hfout will be phase-aligned with the reference clock but at half the frequency, and x2fout will be either phase-aligned at the same frequency as the reference clock if divsel = 0, or at twice the frequency if divsel = 1. enabling outputs the S4405 has two output-enable inputs that control which outputs toggle. when held low, outen0 controls the frequency doubler output x2fout and the half-frequency output hfout. outen1 controls the fout0C3 outputs. when an output enable pin is held high, its associated outputs are disabled and held in a high state. filter the filter output is a tap between the analog out- put of the phase detector and the vco input. this pin allows a simple external filter (figure 2) to be in- cluded in the pll. amcc recommends the use of the filter component values shown. this filter was chosen for its ability to reduce the output jitter and filter out noise on the reference clock input. reset when the reset pin is pulled low, all the internal states go to zero, but the outputs will not go low until one clock cycle later (vco/2 or period of the refer- ence clock). after the chip is reset, the pll requires a resynchronization time before lock is again achieved. lock detect a lock detect function is provided by the lock out- put. when the selected reference clock and fbclk figure 2. external pll filter figure 3. external power supply filter analog +5v 0.1 ? digital +5v digital gnd analog gnd fb1 fb2 10 ? tantalum (optional) are within 2C4 ns of each other, the pll is in lock, and the lock output goes high. power supply considerations power for the analog portion of the S4405 chips must be isolated from the digital power supplies to mini- mize noise on the analog power supply pins. this isolation between the analog and digital power sup- plies can be accomplished with a simple external power supply filter (figure 3). the analog power planes are connected to the digital power planes through single ferrite beads (fb1 and fb2) or induc- tors capable of handling 25 ma. the recommended value for the inductors is in the range from 5 to 100 m h, and depends upon the frequency spectrum of the digital power supply noise. the ferrite beads should exhibit 75 w impedance at 10 mhz. decoupling capacitors are also very important to minimize noise. the decoupling capacitors must have low lead inductance to be effective, so ceramic chip capacitors are recommended. decoupling ca- pacitors should be located as close to the power pins as physically possible. and the decoupling should be placed on the top surface of the board between the part and its connections to the power and ground planes. board layout considerations ? the S4405 is sensitive to noise on the analog +5 v and filter pins. care should be taken during board layout for optimum results. ? all decoupling capacitors (c1Cc4 = 0.1 m f) should be bypassed between vcc and gnd, and placed as close to the chip as possible (preferably using ce- ramic chip caps) and placed on top of board between S4405 and the power and ground plane connections. ? no dynamic signal lines should pass through or beneath the filter circuitry area (enclosed by dashed lines in figure 4) to avoid the possibility of noise due to crosstalk. a +5v 0.1 ? 1.5k w 32 31 S4405 a vcc filter
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 4 ? the analog vcc supply can be a filtered digital vcc supply as shown below. the ferrite beads or inductors, fb1 and fb2, should be placed within three inches of the chip. ? the analog vcc plane should be separated from the digital vcc and ground planes by at least 1/8 inch. S4405 pin descriptions phsel0. this input, along with phsel1, allows se- lection of the phase relationship among the four fout0Cfout3 outputs. see tables 2 and 3 for the selection choices. phsel1. along with phsel0, allows selection of the phase relationship among the four fout0Cfout3 outputs. see tables 2 and 3 for the selection choices. outen0. active low. output enable signal that con- trols which outputs toggle. controls the frequency doubler output (x2fout) and the half-frequency out- put (hfout). outen1. active low. output enable signal that con- trols which outputs toggle. controls the fout0C fout3 outputs. reset. active low. initializes internal states for test purposes. tsten. active high. allows refclk to drive the divider phase adjust circuitry, after the first divide-by- two stage. therefore, refclk can be divided by two in the divide-by-four mode, and divided by four in the divide-by-eight mode, and used to directly sequence the outputs. inpsel. allows user to select between ttlref and peclref reference frequencies. when inpsel is high, the peclref input is selected. output signals filter. a tap between the analog output of the phase detector and the vco input. allows a simple external filter (a single resistor and capacitor) to be included in the pll. x2fout. provides a clock signal identical to the fout0 output in the divide-by-four mode and twice the fout0 frequency (maximum of 80 mhz) in the divide-by-eight mode. fout0. clock output. fout1. clock output. fout2. clock output. fout3. clock output. hfout. provides a clock signal in phase with the fout0 output, but at half the fout0 frequency in both the divide-by-four and divide-by-eight modes. peclp/n. differential pecl output, always one-half the vco frequency. lock. goes high when the reference clock and fbclk are within 2C4 ns of each other, demonstrat- ing that the pll is in lock. test capabilities the tsten input allows users to bypass the vco and provide their own clock through the selected reference clock input. when tsten is high, the vco is turned off and the refclk signal drives the divider/phase adjust circuitry, directly sequencing the outputs. the tsten and refclk inputs join the divider circuitry after the initial divide-by-two stage. therefore, refclk is divided by two in the divide-by-four mode and di- vided by four in the divide-by-eight mode. pin descriptions input signals ttlref. ttl. frequency reference supplied by the user that, along with the output tied to the fbclk input, determines the frequency of the fout0C fout3 outputs. inpsel is used to select between this reference and the pecl reference peclrefp/n. peclrefp/n. differential pecl. frequency refer- ence supplied by the user. selectable by the inpsel input. fbclk. feedback clock that, along with the refer- ence clock input, determines the frequency of the fout0Cfout3 outputs. one output is selected to feed back to this input. (see table 3.) divsel. controls the divider circuit that follows the vco. when divsel is low, the vco frequency is divided by four. when divsel is high, the vco fre- quency is divided by eight. (see tables 1 and 3.) 34 33 32 31 1.5k w 0.1 m f 0.1 m f a +5v d gnd d +5v fb2 fb1 S4405 a gnd figure 4. board layout
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 5 table 3. output select matrix configuration select pins output fed output phase relationships number to fbclk ? 4 ? 8 phsel1 phsel0 fout0 fout1 fout2 fout3 hfout x2fout 1 0 0 fout0Cfout3 0 0 0 0 0/2 0 2(0) 2 0 0 hfout 2(0) 2(0) 2(0) 2(0) 0 2(0) 4(0) 3 0 0 x2fout ( ? 8) 0/2 0/2 0/2 0/2 0/4 0 4 0 1 fout0 0 q 2q 3q 0/2 0 2(0) 5 0 1 fout1 Cq 0 q 2q Cq/2 Cq 2(Cq) 6 0 1 fout2 C2q Cq 0 q C2q/2 C2q 2(C2q) 7 0 1 fout3 C3q C2q Cq 0 C3q/2 C3q 2(C3q) 8 0 1 hfout 2(0) 2(q) 2(2q) 2(3q) 0 2(0) 4(0) 9 0 1 x2fout ( ? 8) 0/2 q/2 2q/2 3q/2 0/4 0 10 1 0 fout0 0 Ct t q 0/2 0 2(0) 11 1 0 fout1 t 0 2t q+t t/2 t 2(t) 12 1 0 fout2 Ct C2t 0 qCt Ct/2 Ct 2(Ct) 13 1 0 fout3 Cq CqCt Cq+t 0 Cq/2 Cq 2(Cq) 14 1 0 hfout 2(0) 2(Ct) 2(t) 2(q) 0 2(0) 4(0) 15 1 0 x2fout ( ? 8) 0/2 Ct/2 t/2 q/2 0/4 0 16 1 1 fout0 0 t 2t 3t 0/2 0 2(0) 17 1 1 fout1 Ct 0 t 2t Ct/2 Ct 2(Ct) 18 1 1 fout2 C2t Ct 0 t C2t/2 C2t 2(C2t) 19 1 1 fout3 C3t C2t Ct 0 C3t/2 C3t 2(C3t) 20 1 1 hfout 2(0) 2(t) 2(2t) 2(3t) 0 2(0) 4(0) 21 1 1 x2fout ( ? 8) 0/2 t/2 2t/2 3t/2 0/4 0 notes: 1. 0 implies the output is aligned with the reference clock. 2. t implies the output lags the reference clock by a minimum phase delay. 3. q implies the output lags the reference clock by 90 of phase. 4. Ct implies the output leads the reference clock by a minimum phase delay. 5. Cq implies the output leads the reference clock by 90 of phase. 6. 2( ) implies the output is at twice the frequency of the reference clock. 7. /2 implies the output is at half the frequency of the reference clock. 8. the pecln/p differential pecl output is not affected by the phsel inputs. 0 t ? 2t ttlref 0 q 2q ? ttlref 2(0) 0/2 0/4 4(0) ttlref 0 90 180 table entry table entry table entry waveform waveform waveform ? t 2t ?0 legend output select matrix S4405
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 6 S4405 electrical characteristics absolute maximum ratings ttl supply voltage vcc (gnd = 0) 7.0 v ttl input voltage (gnd = 0) 5.5 v operating temperature 0 c to 70 c ambient operating junction temperature tj + 130 c storage temperature C65 c to +150 c symbol v ih 2 input high voltage (ttl) 2.0 2.4 2.0 -25 v guaranteed input high voltage for all inputs v il 2 input low voltage (ttl) v ik input clamp diode voltage 0.8 v -1.2 0.5 -0.8 v v v v 10 ? guaranteed input low voltage for all inputs v cc = min, i in = -18ma i i input high current at max 1.0 ma -300 -50 ? ? v cc = max, v in = v cc i os 4 output short circuit current -100 ma v cc = max, v out = 0v i cc static 95 ma v cc = max i cct total i cc (dynamic and static) 200 ma c load = 25pf at 50 mhz i ih input high current v cc = min, v in = 2.7v v cc = min, v in = 0.5v v oh output high voltage v cc = min v ol output low voltage v cc = min i il input low current i oh = -12ma 3 i oh = -24ma 3 i ol = 24ma 3 parameter min typ 1 max units dc test conditions inpsel others dc characteristics (ttl i/o) parameter min nom max units ttl supply voltage (vcc) 4.75 5.0 5.25 v operating temperature 0 70 c (ambient) (ambient) junction temperature 130 c recommended operating conditions dc characteristics (pecl i/o) symbol parameter dc test conditions min typ 1 max units v ih 2 input high voltage (pecl) guaranteed input high voltage v cc C1145 v cc C600 v for all inputs v il 2 input low voltage (pecl) guaranteed input low voltage v cc C2000 v cc C1450 v for all inputs v oh output high voltage v cc C1075 v cc C650 v v ol output low voltage v cc C1980 v cc C1585 v v cc = 5.0 v load = 50 w to v cc C2v 1. typical limits are at 25 c, v cc = 5.0v. 2. these input levels provide zero noise immunity and should only be tested in a static, noise-free environment. 3. i oh /i ol values indicated are for dc test correlation. actual dynamic currents are significantly higher and are optimized to balance rise and fall times. 4. maximum test duration one second.
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 7 ac specifications S4405 table 4. ac specifications symbol description min max min max units f vco vco frequency 160 266 160 320 mhz f ref refclk frequency 10 66 10 80 mhz mpw ref refclk minimum pulse width 5.0 5.0 ns t pe phase error between ttlref and fbclk -1 0 -1 0 ns t pep phase error between peclref and fbclk -3 -1 -3 -1 ns t ped phase error difference from part to part 1 0 750 0 750 ps t skew output skew 2 (ttl) 0 400 0 400 ps t dc output duty cycle 45 55 45 55 % f pecl peclp/n frequency 80 132 80 160 mhz f fout fout frequency 3 (ttl) 20 66 20 80 mhz f hfout hfout frequency 3 10 33 10 40 mhz f 2xfout 2xfout frequency 3 40 66 40 80 mhz t ps nominal phase shift increment 3.75 6.25 3.125 6.25 ns t ofd tpd outen0C2 to fouts, disable 2 7 2 7 ns t ofe tpd outen0C2 to fouts, enable 2 7 2 7 ns t irf input rise/fall time 1 3 1 3 ns t orf fout rise/fall time 4 0.5 1.5 0.5 1.5 ns t lock loop acquisition time 5 55ms S4405b-66 S4405b-80 1. difference in phase error between two parts at the same voltage, temperature and frequency. 2. output skew guaranteed for equal loading at each output. 3. c load = 35 pf. 4. with 35 pf output loading (0.8 v to 2.0 v transition). 5. depends on loop filter chosen. (number given is for example filter.) figure 5. timing waveforms ttlref, peclref ref mpw fbclk fout0? outen0? t pe ref mpw hfout, x2fout t skew t skew t ofd t ofe output valid disabled hfout, x2fout fout0? peclp
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 8 S4405 package information figure 6. S4405 44 plcc package and pinout 1 4 3 2 44 42 41 15 12 13 14 16 17 18 5 6 7 8 9 10 11 25 24 23 22 21 20 19 ttlref fbclk nc dgnd peclrefn peclrefp dgnd d +5v fout2 d +5v dgnd fout1 fout0 d +5v divsel phsel0 phsel1 agnd a+5v a+5v filter outen0 hfout x2fout dgnd outen1 peclp pecln 26 27 28 31 34 33 32 30 29 39 38 37 36 35 40 43 fout3 lock d +5v d +5v dgnd dgnd dgnd dgnd dgnd d +5v dgnd d +5v reset testen nc inpsel all dimensions nominal in inches.
applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333 page 9 ordering information S4405 amcc clock driver products are available in several output skew and shipping configurations. the order number is formed by a combination of: ? device number ? package type ? speed option (if applicable) ? optional shipping configuration S4405 b 66 /td optional shipping configuration blank = 28 unit tube /d = dry pack /td = tape, reel and dry pack speed option ?66 = 66 mhz ?80 = 80 mhz package option b = 44-pin plcc device number example: S4405b?6/d 44-pin plcc package, 66 mhz, dry packed in the standard tube. ordering information amcc is a registered trademark of applied micro circuits corporation. copyright ? 1995 applied micro circuits corporation printed in u.s.a./12-08-95 amcc reserves the right to change specifications for this product in any manner without notice, and substitute devices manufactured to higher grade levels than ordered. applied micro circuits corporation 6195 lusk blvd., san diego, ca 92121 ? (619) 450-9333
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